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SH69P48A otp 4k 4-bit micro-controller with 10-bit sar a/d converter 1 v2.1 features ? sh6610d-based single-chip 4-bit micro-controller with 10-bit sar a/d converter ? otprom: 4k x 16bits ? ram: 253 x 4bits - 61 system control registers - 192 data memory ? operation voltage: - f osc = 30khz - 4mhz, v dd = 2.4v - 5.5v - f osc = 4mhz - 10mhz, v dd = 4.5v - 5.5v ? 17 cmos bi-directional i/o ports plus 1 cmos open drain output port (porte.1) ? 8-level stack (including interrupts) ? two 8-bit auto re-loaded timer/counter one can switch to external clock source ? warm-up timer ? powerful interrupt sources: - a/d interrupt - internal interrupt (timer1, timer0) - external interrupts: portb/d (falling edge) ? oscillator (code option) - crystal oscillator: 32.768khz, 400khz - 10mhz - ceramic resonator: 400khz - 10mhz - external rc oscillator: 400khz - 10mhz - internal rc oscillator: 4mhz 5% - external clock: 30khz - 10mhz ? instruction cycle time (4/f osc ) ? two low power operation modes: halt and stop ? reset - built-in watchdog timer (code option) - built-in power-on reset (por) - built-in low voltage reset (lvr) ? two-level low voltage reset (lvr) (code option) ? 10 channels 10-bit resolution analog/digital converter (adc) ? read rom table function ? 2 channels (8 + 2) bits pwm output ? otp type/code protection ? 20-pin dip/sop, 16-pin sop package general description SH69P48A is a single-chip 4-bit micro-cont roller, that integrates a sh6610d cpu core, 253 nibbles of ram, 4k words of otp rom, two 8-bit timer/counter, 10 channels 10-bit adc, 2 channels (8 + 2) bits high speed pwm output, on-chip oscillator clock circuitry, on-chip watchdog timer, low voltage reset function and support power saving modes to reduce power consumption. the SH69P48A is i deal for charger applications.
SH69P48A 2 pin configuration SH69P48A /20pin 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 20 19 portd.2/t1 portd.3/pwm1 portc.2/pwm0 portc.3/t0 reset/porte.1 gnd porta.0/an0 porta.1/an1 porta.2/an2 v dd portb.3/an7 portb.2/an6 portb.1/an5 osci/porte.0 portc.1/vref osco/portc.0 portd.0/an8 portd.1/an9 10 11 porta.3/an3 portb.0/an4 SH69P48A /16pin 1 2 3 4 5 6 7 8 14 13 12 11 10 9 16 15 portd.2/t1 portd.3/pwm1 portc.2/pwm0 portc.3/t0 reset/porte.1 gnd porta.0/an0 porta.1/an1 v dd portb.3/an7 portb.2/an6 osci/porte.0 portc.1/vref osco/portc.0 portd.0/an8 portd.1/an9
SH69P48A 3 block diagram oscillator cpu wdt rc portc [4 bits] portd [4 bits] otp rom 4096 x 16 bits ram 61 x 4 bits system register timer 0 (8 bits) watchdog timer reset circuit timer1 (8 bits) osci/sck/porte.0 osco/portc.0 v dd gnd reset/ potrte.1 porta [4 bits] an3 - an0 portb [4 bits] an7 - an4 portb.0/an4 portb.1/an5 portb.2/an6 portb.3/an7 ram 192x 4 bits data memory 10ch x 10bits adc 2ch x (8 + 2) bits pwm power circuit portc.1/v ref portc.2/pwm0 portc.3/t0 portd.0/an8 portd.1/an9 portd.2/t1 portd.3/pwm1 adc v ref porta.0/an0 porta.1/an1 porta.2/an2 porta.3/an3 pwm buffer
SH69P48A 4 pin descriptions: pin no. 20 pin 16 pin designation i/o description 1 1 portd.2 - /t1 i/o i i bit programmable bi-directional i/o port vector port interrupt. (falling edge active) shared with timer1 input capture 2 2 portd.3 - /pwm1 i/o i o bit programmable bi-directional i/o port vector port interrupt. (falling edge active) shared with pwm1 output 3 3 portc.2 /pwm0 i/o o bit programmable bi-directional i/o port shared with pwm0 output 4 4 portc.3 /t0 i/o i bit programmable bi-directional i/o port shared with timer0 external clock input 5 5 reset /porte.1 i o reset pin input, (low active) open drain output port (selected by code option) 6 6 gnd p ground pin 7 7 porta.0 /an0 i/o i bit programmable bi-directional i/o port shared with adc input channel an0 8 8 porta.1 /an1 i/o i bit programmable bi-directional i/o port shared with adc input channel an1 9 - porta.2 /an2 i/o i bit programmable bi-directional i/o port shared with adc input channel an2 10 - porta.3 /an3 i/o i bit programmable bi-directional i/o port shared with adc input channel an3 11 - portb.0 - /an4 i/o i i bit programmable bi-directional i/o port vector port interrupt. (falling edge active) shared with adc input channel an4 12 - portb.1 - /an5 i/o i i bit programmable bi-directional i/o port vector port interrupt. (falling edge active) shared with adc input channel an5 13 9 portb.2 - /an6 i/o i i bit programmable bi-directional i/o port vector port interrupt. (falling edge active) shared with adc input channel an6 14 10 portb.3 - /an7 i/o i i bit programmable bi-directional i/o port vector port interrupt. (falling edge active) shared with adc input channel an7 15 11 v dd p power supply pin 16 12 osci /porte.0 i i/o oscillator input pin, connect to crys tal/ceramic oscillator or external resistor of external rc oscillator. bi-directional i/o port in the internal rc mode 17 13 osco /portc.0 o i/o oscillator output pin, connect to crystal/ceramic oscillator. bi-directional i/o port in the rc oscillator mode
SH69P48A 5 pin descriptions: (continued) pin no. 20 pin 16 pin designation i/o description 18 14 portc.1 /v ref i/o i bit programmable bi-directional i/o port shared with external adc v ref input 19 15 portd.0 - /an8 i/o i i bit programmable bi-directional i/o port vector port interrupt (falling edge active) shared with adc input channel an8 20 16 portd.1 - /an9 i/o i i bit programmable bi-directional i/o port vector port interrupt (falling edge active) shared with adc input channel an9 otp programming pin description (otp program mode) pin no. 20 pin 16 pin symbol i/o shared by description 15 11 v dd p v dd programming power supply (+5.5v) 5 5 v pp p reset programming high voltage power supply (+11v) 6 6 gnd p gnd ground 16 12 sck i osci/porte.0 programming clock input pin 7 7 sda i/o porta.0/an 0 programming data pin
SH69P48A 6 functional description 1. cpu the cpu contains the followi ng functional blocks: program counter (pc), arithmetic logic unit (alu), carry flag (cy), accumulator, table branch register, data pointer (inx, dph, dpm, and dpl) and stacks. 1.1. pc the pc is used for rom addressing consisting of 12-bit: page register (pc11), and ripple carry counter (pc10, pc9, pc8, pc7, pc6, pc5, pc4, pc3, pc2, pc1, pc0). the program counter is loaded with data corresponding to each instruction. the unconditi onal jump instruction (jmp) can be set at 1-bit page register for higher than 2k. the program counter cans on ly 4k program rom address. (refer to the rom description). 1.2. alu and cy the alu performs arithmetic and logic operations. the alu provides the following functions: binary addition/subtraction (adc, sbc, add, sub, adi, sbi) decimal adjustments for addition/subtraction (daa, das) logic operations (and, eor, or, andim, eorim, orim) decisions (ba0, ba1, ba2, ba3, baz, bnz, bc, bnc) logic shift (shr) the carry flag (cy) holds the alu overflow that the arithmetic operation generates. during an interrupt service or call instruction, the carry flag is pushed into the stack and recovered from the stack by the rtni instruction. it is unaffected by the rtnw instruction. 1.3. accumulator (ac) the accumulator is a 4-bit register holding the results of the arithmetic logic unit. in conjunction with the alu, data is transferred between the accumulator and system register, or data memory can be performed. 1.4. table branch register (tbr) table data can be stored in program memory and can be referenced by using table branch (tjmp) and return constant (rtnw) instructions. the tbr and ac are placed by an offset address in program rom. tjmp instruction branch into address ((pc11 - pc8) x (2 8 ) + (tbr, ac)). the address is determined by rtnw to return look-up value into (tbr, ac). rom code bit7-bit4 is placed into tbr and bit3-bit0 into ac. 1.5. data pointer the data pointer can indirectly address data memory. pointer address is located in register dph (3-bit), dpm (3-bit) and dpl (4-bit). the addressing range can have 3ffh locations. pseudo index address (inx) is used to read or write data memory, then ram address bit9 - bit0 which comes from dph, dpm and dpl. 1.6. stack the stack is a group of regist ers used to save the contents of cy & pc (11-0) sequentially with each subroutine call or interrupt. the msb is saved for cy and it is organized into 13 bits x 8 levels. the stack is operated on a first-in, last-out basis and returned sequentially to the pc with the return instructions (rtni/rtnw). note: the stack nesting includes both subroutine calls and interrupts requests. the maximum allowed for subroutine calls and interrupts are 8 levels. if the number of calls and interrupt requests exceeds 8, then the bottom of stack will be shifted out, that program execution may enter an abnormal state. 2. ram built-in ram contains general-purpose data memory and system register. because of its stat ic nature, the ram can keep data after the cpu enters stop or halt. 2.1. ram addressing data memory and system register can be accessed in one inst ruction by direct addressing. the following is the memory allocation map: system register and i/o: $000 - $02f, $380 - $38c data memory: $030 - $0ef 2.2. configuration of system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $00 iead iet0 iet1 iep r/ w interrupt enable flags $01 irqad irqt0 irqt1 irqp r/w interrupt request flags $02 t0s t0m.2 t0m.1 t0m.0 r/w bit2 - 0: timer0 mode register bit3: t0 signal source $03 t1e t1m.2 t1m.1 t1m.0 r/w bit2 - 0: timer1 mode register bit3: t1 external signal edge select $04 t0l.3 t0l.2 t0l.1 t0l. 0 r/w timer0 load/counter register (low nibble) $05 t0h.3 t0h.2 t0h.1 t0h.0 r/w timer0 load/counter register (high nibble) $06 t1l.3 t1l.2 t1l.1 t1l. 0 r/w timer1 load/counter register (low nibble)
SH69P48A 7 2.2. configuration of system register: (continued) address bit 3 bit 2 bit 1 bit 0 r/w remarks $07 t1h.3 t1h.2 t1h.2 t1h.0 r/w timer1 load/counter register (high nibble) $08 pa.3 pa.2 pa.1 pa.0 r/w porta in 16 pin mode, bit2 - 3 are reserved; always keep it to ?0? in the user?s program refer to i/o notice $09 pb.3 pb.2 pb.1 pb.0 r/w portb in 16 pin mode, bit0 - 1 are reserved, always keep it to ?0? in the user?s program refer to i/o notice $0a pc.3 pc.2 pc.1 pc.0 r/w portc $0b pd.3 pd.2 pd.1 pd.0 r/w portd $0c - - pe.1 pe.0 r/w porte $0d - - - - - reserved $0e tbr.3 tbr.2 tbr.1 tbr. 0 r/w table branch register $0f inx.3 inx.2 inx.1 inx.0 r/w pseudo index register $10 dpl.3 dpl.2 dpl.1 dpl.0 r/w data pointer for inx low nibble $11 - dpm.2 dpm.1 dpm.0 r/w data pointer for inx middle nibble $12 - dph.2 dph.1 dph.0 r/w data pointer for inx high nibble $13 t1go dec - tm1s0 r/w bit0: set timer1 mode bit2: select directive edge active enable bit3: set timer1 function start $14 vrefs - - adcon r/w bit0: set adc module operate bit3: select internal/external reference voltage $15 go/ done tadc1 tadc0 adcs r/w bit0: set adc conversion time bit2, bit1: select adc clock period bit3: adc status flag $16 acr3 acr2 acr1 acr0 r/w bit3 - 0: adc port configuration control $17 ch3 ch2 ch1 ch0 r/w bit3 - 0: select adc channel $18 pacr.3 pacr.2 pacr.1 pacr.0 r/w porta input/output control in 16 pin mode, bit2 - 3 are reserved, always keep it to ?1? in the user?s program refer to i/o notice $19 pbcr.3 pbcr.2 pbcr.1 pbcr.0 r/w portb input/output control in 16 pin mode, bit0 - 1 are reserved, always keep it to ?1? in the user?s program refer to i/o notice
SH69P48A 8 2.2. configuration of system register: (continued) address bit 3 bit 2 bit 1 bit 0 r/w remarks $1a pccr.3 pccr.2 pccr.1 pccr.0 r /w portc input/output control $1b pdcr.3 pdcr.2 pdcr.1 pdcr.0 r /w portd input/output control $1c - - - pecr.0 r/w porte input/output control $1d - - - - - reserved $1e - wdt wdt.2 - wdt.1 - wdt.0 - r/w r bit2 - 0: watchdog timer control bit3: watchdog timer overflow flag (read only) $1f - - - - - reserved $20 pwm0s t0ck1 t0ck0 pwm0_en r/w bit0: pwm0 output enable bit2, bit1: sele ct pwm0 clock bit3: set pwm0 output mode of duty cycle $21 pwm1s t1ck1 t1ck0 pwm1_en r/w bit0: pwm1 output enable bit2, bit1: sele ct pwm1 clock bit3: set pwm1 output mode of duty cycle $22 pp0.3 pp0.2 pp0.1 pp0.0 r/w pwm0 period low nibble $23 pp0.7 pp0.6 pp0.5 pp0.4 r/w pwm0 period high nibble $24 - - pdf0.1 pdf0.0 r/w pwm0 duty fine tune nibble $25 pd0.3 pd0.2 pd0.1 pd0.0 r/w pwm0 duty low nibble $26 pd0.7 pd0.6 pd0.5 pd0.4 r/w pwm0 duty high nibble $27 pp1.3 pp1.2 pp1.1 pp1.0 r/w pwm1 period low nibble $28 pp1.7 pp1.6 pp1.5 pp1.4 r/w pwm1 period high nibble $29 - - pdf1.1 pdf1.0 r/w pwm1 duty fine tune nibble $2a pd1.3 pd1.2 pd1.1 pd1.0 r/w pwm1 duty low nibble $2b pd1.7 pd1.6 pd1.5 pd1.4 r/w pwm1 duty high nibble $2c - - - - - reserved $2d - - a1 a0 r adc data low nibble (read only) $2e a5 a4 a3 a2 r adc data medium nibble (read only) $2f a9 a8 a7 a6 r adc data high nibble (read only) $380 rdt.3 rdt.2 rdt.1 rdt.0 r/w rom data table address/data register $381 rdt.7 rdt.6 rdt.5 rdt.4 r/w rom data table address/data register $382 rdt.11 rdt.10 rdt.9 rdt.8 r/w rom data table address/data register $383 rdt.15 rdt.14 rdt.13 rdt.12 r/w rom data table address/data register $384 pdien.3 pdien.2 pdien.1 pdien. 0 r/w portd interrupt enable flags $385 pdif.3 pdif.2 pdif.1 pdif.0 r/w portd interrupt request flags $386 pbien.3 pbien.2 pbien.1 pbien.0 r/w portb interrupt enable flags $387 pbif.3 pbif.2 pbif.1 pbif.0 r/w portb interrupt request flags $388 ppacr.3 ppacr.2 ppacr.1 ppacr.0 r/w porta pull-high control $389 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr.0 r/w portb pull-high control $38a pp ccr.3 ppccr.2 ppccr.1 ppccr.0 r/w portc pull-high control $38b pp dcr.3 ppdcr.2 ppdcr.1 ppdcr.0 r/w portd pull-high control $38c - - - ppecr.0 r/w porte pull-high control
SH69P48A 9 3. rom the rom can address 4096 x 16 bits of program area from $0000 to $0fff. 3.1. vector address area ($000 to $004) the program is sequentially exec uted. there is an area address $000 through $004 that is reserved for a special interrupt service routine such as starting vector address address instruction remarks $000 jmp* jump to reset service routine $001 jmp* jump to adc interrupt service routine $002 jmp* jump to timer0 interrupt service routine $003 jmp* jump to timer1 interrupt service routine $004 jmp* jump to portb/d interrupt service routine *jmp instruction can be repl aced by any instruction. 3.2. rom data table system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $380 rdt.3 rdt.2 rdt.1 rdt.0 r/w rom data table address/data register $381 rdt.7 rdt.6 rdt.5 rdt.4 r/w rom data table address/data register $382 rdt.11 rdt.10 rdt.9 rdt.8 r/w rom data table address/data register $383 rdt.15 rdt.14 rdt.13 rdt.12 r/w ro m data table address/data register the rdt register consists of a 12-bit write-only pc address load register (rdt.11 - rdt.0) and a 16-bit read-only rom table data read-out register (rdt.15 - rdt.0). to read out the rom table data, users should write the rom tabl e address to the rdt register first (high nibble first then low nibble), then, after one instruction, the right data will be put into the rdt register automatic ally (write the lowest nibb le of address into the register will start the data read-out action).
SH69P48A 10 4. initial state 4.1. system register state: address bit 3 bit 2 bit 1 bit 0 power-on reset /pin reset /low voltage reset wdt reset $00 iead iet0 iet1 iep 0000 0000 $01 irqad irqt0 irqt1 irqp 0000 0000 $02 t0s t0m.2 t0m.1 t0m.0 0000 uuuu $03 t1e t1m.2 t1m.1 t1m.0 0000 uuuu $04 t0l.3 t0l.2 t0l.1 t0l.0 xxxx xxxx $05 t0h.3 t0h.2 t0h.1 t0h.0 xxxx xxxx $06 t1l.3 t1l.2 t1l.1 t1l.0 xxxx xxxx $07 t1h.3 t1h.2 t1h.1 t1h.0 xxxx xxxx $08 pa.3 pa.2 pa.1 pa.0 0000 0000 $09 pb.3 pb.2 pb.1 pb.0 0000 0000 $0a pc.3 pc.2 pc.1 pc.0 0000 0000 $0b pd.3 pd.2 pd.1 pd.0 0000 0000 $0c - - pe.1 pe.0 --10 --10 $0d - - - - ---- ---- $0e tbr.3 tbr.2 tb r.1 tbr.0 xxxx uuuu $0f inx.3 inx.2 inx.1 inx.0 xxxx uuuu $10 dpl.3 dpl.2 dpl. 1 dpl.0 xxxx uuuu $11 - dpm.2 dpm.1 dpm.0 -xxx -uuu $12 - dph.2 dph.1 dph.0 -xxx -uuu $13 t1go dec - tm1s0 00-0 0u-u $14 vrefs - - adcon 0?0 u?0 $15 go/ done tadc1 tadc0 adcs 0000 0uuu $16 acr3 acr2 acr1 acr0 0000 uuuu $17 ch3 ch2 ch1 ch0 0000 uuuu $18 pacr.3 pacr.2 pacr.1 pacr.0 0000 0000 $19 pbcr.3 pbcr.2 pbcr. 1 pbcr.0 0000 0000 $1a pccr.3 pccr.2 p ccr.1 pccr.0 0000 0000 $1b pdcr.3 pdcr.2 p dcr.1 pdcr.0 0000 0000 $1c - - - pecr.0 ---0 ---0 $1d - - - - ---- ---- $1e wdt wdt.2 wdt.1 wdt.0 0000 1000 $1f - - - - ---- ---- $20 pwm0s t0ck1 t0ck0 pwm0_en 0000 uuu0 legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
SH69P48A 11 system register state: (continued) address bit 3 bit 2 bit 1 bit 0 power-on reset /pin reset /low voltage reset wdt reset $21 pwm1s t1ck1 t1ck0 pwm1_en 0000 uuu0 $22 pp0.3 pp0.2 pp0.1 pp0.0 xxxx uuuu $23 pp0.7 pp0.6 pp0.5 pp0.4 xxxx uuuu $24 - - pdf0.1 pdf0.0 --xx --uu $25 pd0.3 pd0.2 pd0.1 pd0.0 xxxx uuuu $26 pd0.7 pd0.6 pd0.5 pd0.4 xxxx uuuu $27 pp1.3 pp1.2 pp1.1 pp1.0 xxxx uuuu $28 pp1.7 pp1.6 pp1.5 pp1.4 xxxx uuuu $29 - - pdf1.1 pdf1.0 --xx --uu $2a pd1.3 pd1.2 pd 1.1 pd1.0 xxxx uuuu $2b pd1.7 pd1.6 pd 1.5 pd1.4 xxxx uuuu $2c - - - - ---- ---- $2d - - a1 a0 --xx --uu $2e a5 a4 a3 a2 xxxx uuuu $2f a9 a8 a7 a6 xxxx uuuu $380 rdt.3 rdt.2 rdt.1 rdt.0 xxxx uuuu $381 rdt.7 rdt.6 rdt.5 rdt.4 xxxx uuuu $382 rdt.11 rdt.10 rdt.9 rdt.8 xxxx uuuu $383 rdt.15 rdt.14 rdt .13 rdt.12 xxxx uuuu $384 pdien.3 pdien.2 pdien.1 pdien.0 0000 0000 $385 pdif.3 pdif.2 pdif.1 pdif.0 0000 0000 $386 pbien.3 pbien.2 pbi en.1 pbien.0 0000 0000 $387 pbif.3 pbif.2 pbif.1 pbif.0 0000 0000 $388 ppacr.3 ppacr.2 ppacr.1 ppacr.0 0000 0000 $389 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr.0 0000 0000 $38a ppccr.3 ppccr.2 pp ccr.1 ppccr.0 0000 0000 $38b ppdcr.3 ppdcr.2 pp dcr.1 ppdcr.0 0000 0000 $38c - - - ppecr.0 ---0 ---0 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. 4.2. others initial states: others after any reset program counter (pc) $000 cy undefined accumulator (ac) undefined data memory undefined
SH69P48A 12 5. system clock and oscillator the oscillator generates the basic clock pulses that prov ide the system clock to supply cpu and on-chip peripherals. system clock = f osc /4 5.1. instruction cycle time: (1) 4/32.768khz ( 122.1 s) for 32.768khz oscillator. (2) 4/10mhz (= 0.4 s) for 10mhz oscillator. 5.2. oscillator type (1) crystal oscillator: 32.768khz or 400khz - 10mhz osci osco c1 c2 crystal (2) ceramic resonator: 400khz - 10mhz osci osco c1 c2 ceramic capacitor selection for oscillator ceramic resonators frequency c1 c2 recommend type manufacturer 455khz 47 - 100pf 47 - 100pf zt 455e jingbo electronic shenzhen 3.58mhz - - zt 3.58m* jingbo electronic shenzhen 4mhz - - zt 4m* jingbo electronic shenzhen *- the specified ceramic resonator has internal built-in load capacity crystal oscillator frequency c1 c2 recommend type manufacturer 32.768khz 5 - 12.5pf 5 - 12.5pf dt 38 ( 3 x 8) kds 4mhz 8 - 15pf 8 - 15pf 49s-4.000m-f16e jingbo electronic shenzhen 8mhz 8 - 15pf 8 - 15pf 49s-8.000m-f16e jingbo electronic shenzhen notes: 1. capacitor values are used for design guidance only! 2. these capacitors were tested with the crys tals listed above for basic start-up and operation. they are not optimized. 3. be careful for the stray capacitance on pcb board, the us er should test the performanc e of the oscillator over the expected v dd and the temperature range for the application. before selecting crystal/ceramic, the user should consult the crystal/ceramic manufacturer for appropriate value of external component to get best performance, visit http://www.sinowealth.com for more recommended manufactures. (3) rc oscillator: 400khz - 10mhz osci r osc v dd osco/portc.0 external rc oscillator osci/porte.0 osco/portc.0 internal rc oscillator (f osc = 4mhz 5%) (4) external input clock: 30khz - 10mhz osci external clock source osco/portc.0 note: - if the rc oscillator or the external input clock is sele cted, osco pin will be used as the i/o port (portc.0). - if the internal rc oscillator is selected, osco pin will be used as the i/o port (portc .0), and osci pin will be used as the porte.0.
SH69P48A 13 6. i/o ports ? the mcu provides 17 bi-directional i/o ports plus 1 cmos open drain output port (porte.1 ). the port data put in register ($08 - $0c). the port control re gister ($18 - $1c) controls the port as input or output. each i/o port (excluding those open drain output ports) contains a pull -high resistor, which is controlled by t he value of the corresponding bit in the port pull-high control register ($388 - $38c), independently. ? when the port is selected as an input port, it can turn on the pull-high resistor by writing ?1?, and turn off the pull-high resistor by writing ?0?, to the relevant bit in the port pull-high control register ($388 - $38c). ? when the port is selected as an output port, the pull-high resistor will be turned of f automatically, regardless the value of the corresponding bit in the port pull- high control register ($388 - $38c). ? when portb/d is selected as the digital i nput direction, it can activate port inte rrupt by falling edge (if port interrupt is enabled). system register $08 - $0c:port data register address bit 3 bit 2 bit 1 bit 0 r/w remarks $08 pa.3 pa.2 pa.1 pa.0 r/w porta $09 pb.3 pb.2 pb.1 pb.0 r/w portb $0a pc.3 pc.2 pc.1 pc.0 r/w portc $0b pd.3 pd.2 pd.1 pd.0 r/w portd $0c - - pe.1 pe.0 r/w porte note: in 16 pin mode, bit2 - 3 of the $08 ram and bit0 - 1 of the $ 09 ram are reserved; always keep it ?0? in the user?s program. system register $18 - $1c: port control register address bit 3 bit 2 bit 1 bit 0 r/w remarks $18 pacr.3 pacr.2 pacr.1 pacr.0 r/w porta input/output control $19 pbcr.3 pbcr.2 pbcr.1 pbcr.0 r/w portb input/output control $1a pccr.3 pccr.2 pccr.1 pccr.0 r /w portc input/output control $1b pdcr.3 pdcr.2 pdcr.1 pdcr.0 r /w portd input/output control $1c - - - pecr.0 r/w porte input/output control note: in 16 pin mode, bit2 - 3 of the $18 ram and bit0 - 1 of the $19 ram are reserved, always keep it ?1? in the user?s program. pa (/b/c/d/e) cr.n, (n = 0, 1, 2, 3) 0: set i/o as an input direction. (default) 1: set i/o as an output direction. system register $388 - $38c: port pull-high control register address bit 3 bit 2 bit 1 bit 0 r/w remarks $388 ppacr.3 ppacr.2 ppacr.1 ppa cr.0 r/w porta pull-high control $389 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr. 0 r/w portb pull-high control $38a ppccr.3 ppccr.2 ppccr.1 ppccr. 0 r/w portc pull-high control $38b ppdcr.3 ppdcr.2 ppdcr.1 ppdcr. 0 r/w portd pull-high control $38c - - - ppecr.0 r/w porte pull-high control ppa (/b/c/d/e) cr.n, (n = 0, 1, 2, 3) 0: disable internal pull-high resistor. (default) 1: enable internal pull-high resistor.
SH69P48A 14 equivalent circuit for a single i/o pin i/o control register data register pull high register m2t1 0 1 s read data in data read i/o pin pull high v dd gnd v dd ? in SH69P48A, each output port contains a latch, which can hold the output data. writing the port data register (pdr) under the output mode can directly trans fer data to the corresponding pad. all input ports do not have latches, so the external input data should be held externally until the input data is read from outside or reading the port data register (pdr) is read under the input mode. when a digital i/o port is selected as an outpu t, the reading of the associated port bit actually represents the value of the output data latch, not the voltage on the pad. when a digital i/o port is selected as an input, the reading of the associated port bit represents the status on the corresponding pad. ? porta.0 - 3 can be shared with adc input channel (an0 - 3). ? portb.0 - 3 can be shared with adc input channel (an4 - 7). ? portd.0 - 1 can be shared with adc an8-9 input channel (an8 - 9). ? the osco pin can be shared with portc. 0, if the SH69P48A uses the external cl ock or the rc oscillator as the system oscillation. (refer to the code option (op_osc [2:0]).) ? the osci pin can be shared with porte. 0, if the SH69P48A uses the internal rc oscillator as the system oscillation. (refer to the code option (op_osc [2:0]).) ? the reset pin can be shared with porte.1 for open drain output. (refer to the otp option (op_rst).) port interrupt the portb and portd are used as exter nal port interrupt sources. since port b and portd are bi t programmable i/os, only the voltage transition from v dd to gnd applying to the digital input port can generate a port interrupt. the analog input cannot generate any interrupt request. the interrupt control flags are mapped on $385, $387 of the system register. they can be accessed or tested by the read/write operation. those flags are cleared to ?0? at the initialization by the chip reset. port interrupts (including other external interrupt sources) can be used to wake up the cpu from the halt or the stop mode.
SH69P48A 15 system register $384, $386: port interrupt enable flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $384 pdien.3 pdien.2 pdien.1 pdien. 0 r/w portd interrupt enable flags $386 pbien.3 pbien.2 pbien.1 pbien.0 r/w portb interrupt enable flags pdien.n, pbien.n (n = 0, 1, 2, 3) 0: disable port interrupt. (default) 1: enable port interrupt. system register $385, $387: port interrupt request flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $385 pdif.3 pdif.2 pdif.1 pdif.0 r/w portd interrupt request flags $387 pbif.3 pbif.2 pbif.1 pbif.0 r/w portb interrupt request flags pdif.n, pbif.n (n = 0, 1, 2, 3) 0: port interrupt is not present. (default) 1: port interrupt is present. only writing these bits to 0 is available. following is the port interrupt function block-diagram for reference. portb.n portd.n falling edge detector pbien.n pdien.n pbcr.n pdcr.n irqp iep port interrupt note: n = 0, 1, 2, 3 pbif.n pdif.n port interrupt function block-diagram port interrupt programming notes: when the port falling edge is active, any i/o input pin transition from v dd to gnd will set pif.n to ?1?. meanwhile, if the pien.n = 1, the port will generate an interrupt request (irqp = 1). port interrupt can wake the cpu from the halt or stop mode.
SH69P48A 16 adc converter enable register $14: address bit 3 bit 2 bit 1 bit 0 r/w remarks $14 vrefs - - adcon r/w bit0: set adc module operate bit3: select internal/external reference voltage x - - 0 r/w disable the adc converter module. (default) x - - 1 r/w enable the adc converter module. when an adc converter is disabled, po rta.0-3, portb.0-3 and po rtd.0-1 are used as normal i/o ports. when an adc converter is enabled, set the adc port c onfiguration register ($16) to select anyone of porta.0- 3, portb.0-3 and portd.0-1 as a normal i/o port or adc port. for detail, refer to adc converter description. portc.1 can be shared with the reference voltage input (v ref ). adc port configuration control register $14: address bit 3 bit 2 bit 1 bit 0 r/w remarks $14 vrefs - - adcon r/w bit0: set adc module operate bit3: select internal/external reference voltage 0 - - x r/w set portc.1 as a normal i/o port (default) 1 - - x r/w set portc.1 as the external reference voltage input portc.2 can be shared with the pwm0 output (pwm0). pwm0 control register $20: address bit 3 bit 2 bit 1 bit 0 r/w remarks $20 pwm0s t0ck1 t0ck0 pwm0_en r/w bit0: pwm0 output enable bit2, bit1: sele ct pwm0 clock bit3: set pwm0 output mode of duty cycle x x x 0 r/w set portc.2 as a normal i/o port and disable pwm0 (default) x x x 1 r/w set po rtc.2 as pwm0 output and enable pwm0
SH69P48A 17 portc.3 can be shared with the timer0 external input (t0). timer0 mode register $02: address bit 3 bit 2 bit 1 bit 0 r/w remarks $02 t0s t0m.2 t0m.1 t0m.0 r/w bit2-0: timer0 mode register bit3: t0 signal source 0 x x x r/w set portc.3 as a normal i/o port (default) 1 x x x r/w set po rtc.3 as t0 input (falling edge active) portd.2 can be shared with the timer1 input capture. (t1) timer1 control register $13: address bit 3 bit 2 bit 1 bit 0 r/w remarks $13 t1go dec - tm1s0 r/w bit1-0: timer1 mode select x x - 0 r/w set portd.2 as a normal i/o port (default) x x - 1 r/w set port d.2 as t1 input portd.3 can be shared with the pwm1 output (pwm1). pwm1 control register $21: address bit 3 bit 2 bit 1 bit 0 r/w remarks $21 pwm1s t1ck1 t1ck0 pwm1_en r/w bit0: pwm1 output enable bit2, bit1: sele ct pwm1 clock bit3: set pwm1 output mode of duty cycle x x x 0 r/w set portd.3 as a normal i/o port and disable pwm1 (default) x x x 1 r/w set po rtd.3 as pwm1 output and enable pwm1
SH69P48A 18 7. timer 7.1. timer0 SH69P48A has two 8-bit timers. the timer0 has the following features: - 8-bit up-counting timer/counter. - automatic re-loads counter. - 8-level pre-scale. - interrupt on overflow from $ff to $00. the following is a simplified timer0 block diagram. prescaler system clock tosc sync 8-bit counter t0m.2 t0m.0 t0m.1 t0s t0 mux the timer0 provides the following functions: - programmable interval timer function. - read counter value. 7.1.1. timer0 confi guration and operation the timer0 consist of an 8-bit write-only timer load register (tl0l, tl0h) and an 8-bit read-only timer counter (tc0l, tc0h). each of them has low order digits and high order digits. writing data into the timer load register (tl0l, tl0h) can initialize the timer counter. the low-order digit should be written first, and then the high-order digit. the timer counter is automatically loaded with the contents of the load register when the high order digit is written or counter counts overflow from $ff to $00. timer load register: since the register h controls the physical read and write operations. please follow these steps: write operation: low nibble first high nibble to update the counter read operation: high nibble first low nibble followed. load reg. h 8-bit timer counter load reg. l latch reg. l 7.1.2. timer0 mode register the timer0 can be programmed in several different pre scalers by setting the timer0 mode register (tm0). the 8-bit counter prescaler overflow output pulses. the timer0 m ode register is a 3-bit register used for the timer control as shown bellow. these mode registers select the input pulse sources into the timer. timer0 mode register: $02 tm0.2 tm0.1 tm0.0 prescaler divide ratio clock source 0 0 0 /2 11 system clock/t0 0 0 1 /2 9 system clock/t0 0 1 0 /2 7 system clock/t0 0 1 1 /2 5 system clock/t0 1 0 0 /2 3 system clock/t0 1 0 1 /2 2 system clock/t0 1 1 0 /2 1 system clock/t0 1 1 1 /2 0 system clock/t0
SH69P48A 19 external clock/event t0 as timer0 source when external clock/event t0 input as timer0 source, it is sy nchronized with the cpu system clock. the external source must follow certain constraints. the system clock samples it in instruction frame cycl e. therefore it is necessary to be high (at least 2 t osc ) and low (at least 2 t osc ). when the pre-scale ratio selects /2 0 , it is the same as the system clock input. the requirement is as follows: t0h (t0 high time) 2 * t osc + ? t t0l (t0 low time) 2 * t osc + ? t; ? t = 20ns when another pre-scale ratio is selected, the tm0 is scaled by the asynchronous ripple counter and so the pre-scale output is symmetrical. then: 2 t0 * n time low t0 time high t0 = = where: t0 = timer0 input period n = pre-scale value the requirement is: t t * 2 2 t0 * n osc ? + or n t * 2 t * 4 t0 osc ? + so, the limitation is applied for the t0 period time only. the pulse width is not limited by this equation. it is summarized as follows: n t * 2 t * 4 period timer0 t0 osc ? + = timer0 mode register: $02 address bit 3 bit 2 bit 1 bit 0 r/w remarks $02 t0s t0m.2 t0m.1 t0m.0 r/w bit3: t0 signal source 0 x x x r/w shared with portc.3, timer0 source is system clock (default) 1 x x x r/w shared with t0 input, timer0 source is t0 input clock (falling edge active)
SH69P48A 20 7.2. timer1 the timer1 has the following features: - 8-bit up-counting timer/counter. - automatic re-loads counter. - 8-level pre-scale. - interrupt on overflow from $ff to $00. the following is a simplified timer1 block diagram. prescaler system clock tosc sync 8-bit counter t1m.2 t1m.0 t1m.1 eor t1e tm1s0 t1 mux the timer1 provides the following functions: - programmable interval timer function. - read counter value. 7.2.1. timer1 confi guration and operation timer1 consists of a 8-bit write-only timer load register (tl1l, tl1h) and a 8-bit read-only timer counter (tc1l, tc1h). each of them has low order digits and high order digits. writing data into the timer load register (tl1l, tl1h) can initialize the timer counter. the low-order digit should be written first, and then the high-order digit. the timer counter is automatically loaded with the contents of the load register when the high order digit is written or the counter counts overflow from $ff to $00. timer load register: since the register h controls the physical read and write operations. please follow these steps: write operation: low nibble first high nibble to update the counter read operation: high nibble first low nibble followed. load reg. h 8-bit timer counter load reg. l latch reg. l latch reg. h 7.2.2. timer1 control register the timer1 can be programmed in two modes: timer and pulse width measurement. timer1 control register: $13 address bit 3 bit 2 bit 1 bit 0 r/w remarks $13 t1go dec - tm1s0 r/w bit0: timer1 control register x x - 0 r/w timer with internal system clock x x - 1 r/w pulse width measurement (t1 pin input) 0 x - x r/w timer/counter stops (read: status; write: command) (default) 1 x - x r/w timer/counter starts (read: status; write: command) (a) timer mode in this mode, timer1 is performed using the internal clock. the contents of the timer1 counter register ($06 - $07) are loaded into the up-counter while the highest nibble ($07) has been written. the up counter will start counting if the t1go (bit3) in the timer1 control register ($13) is set to 1. the timer1 interrupt will be issued when the up counter overflows from $ff to $00 if the interrupt enable register ($00) bit1 (iet1) is set to 1. after the t1go (bit3) in the timer1 control register ($13) has been set to 1, writing the timer1 counter register ($06 - $07) can?t affect the up counter operating an ymore. only when the t1go (bit3) in th e timer1 control register ($13) has been reset to 0, will the revised contents of the timer1 counter register ($06 - $07) be loaded into the up-counter while the highes t nibble ($07) is written.
SH69P48A 21 timer1 mode register: $03 address bit 3 bit 2 bit 1 bit 0 r/w remarks $03 t1e t1m.2 t1m.1 t1m.0 r/w bit2-0: timer1 mode register bit3: t1 external signal edge select x 0 0 0 r/w timer clock: system clock/2 11 x 0 0 1 r/w timer clock: system clock/2 9 x 0 1 0 r/w timer clock: system clock/2 7 x 0 1 1 r/w timer clock: system clock/2 5 x 1 0 0 r/w timer clock: system clock/2 3 x 1 0 1 r/w timer clock: system clock/2 2 x 1 1 0 r/w timer clock: system clock/2 1 x 1 1 1 r/w timer clock: system clock/2 0 0 x x x r/w t1 input falling edge active (default) 1 x x x r/w t1 input rising edge active (b) pulse width measurement mode in this mode, timer1 is performed using a special function under the timer mode in which counting is started on an edge of the pulse waveform that is input to the t1 pin. it is possible to measure the width of the pulse waveform by reading the up-counter values on state transitions of the input to the t1 pin. the rising or falling edge of the t1 pin input is selected b y setting the t1e (bit3) in the timer1 mode register ($03). but th e source clock of the up counte r is an internal clock selected by properly setting the t1m (bit2-0) in the timer1 mode register ($03). when the t1go (bit3) in the timer1 control register ($13) is set to ?1?, the contents of the up counter must reset to ?00h?, automatically. then a rising (falling) edge signal on the t1 input pin triggers the up counter to start counting. at th e next falling (rising) edge, the counter value is loaded to the timer1 counter register ($06 - $07), individually. simultaneously, the timer1 interrupt will be generated if the interrupt enab le register ($00) bit1 (iet1) is set to 1. when dec (bit2) in the timer1 control register ($13) is 0, the timer1 is in the one-edge capture operation. if the rising edge is selected as the counter-trigging signal, at the next falling edge, the timer1 interrupt request will be generated. at the sa me time, the contents of the up-counter must be loaded to the ti mer1 counter register ($06 - $07) at first and then will be cleared again and the counter will halted. when the next rising edge applies to the t1 input pin, the up counter will start counting for another measurement cycle. when dec (bit2) in the timer1 control register ($13) is 1, the timer1 is in the double-edge capture operation. if the rising edge is selected as the counter- trigging signal, at the next falling edge, the timer1 interrupt request will be generated. at the same time, the contents of the up-counter must be loaded to the timer1 counter register ($06 - $07) at first and then the counter will continue counting. when the next rising edge applies to the t1 input pin, the timer1 interrupt request is also generated. at this time, the contents of the up-counter must be loaded to the timer1 counter register ($06 - $07) again, then the counter must be cleared and can be continue d to start counting following measurement cycles. in this mode, writing the timer1 counter register ($06 ~ $07) at any time can?t affect the up counter operating anymore. in this mode, the t1 pin input signal must follow certain constraints. so, the limitation is applied for the t1 period time described as follows: t1 (period time) 1 * t timer clock + 2 * ? t; ? t= 20ns t1 (period time) ( m * t osc ) + 2 * ? t where m (pre-scale value for timer1 internal clock) =2 0 , 2 1 , 2 2 , 2 3 , 2 5 , 2 7 , 2 9 or 2 11 but, in order to correctly get the pulse measurement value in programming, a sufficient ?wait time? is required for the relevan t timer1 interrupt subroutine program.
SH69P48A 22 timer1 counter register: $06 - $07 address bit 3 bit 2 bit 1 bit 0 r/w remarks $06 t1l.3 t1l.2 t1l.1 t1l.0 r/w timer1 load/counter register (low nibble) $07 t1h.3 t1h.2 t1h.2 t1h.0 r/w timer1 load/counter register (high nibble) t1 internal clock m up-counter t1go timer1 int one edge capture ( dec = 0 ) count start count start t1 counter reg. xx n 00 01 02 00 n 00 01 n - 1 capture capture m t1 internal clock 02 00 01 t m 0001 t - 1 t + 1 up-counter t1go timer1 int double edge capture ( dec = 1 ) count start count start m+1 m t1 counter reg. xx n t capture capture 0 n capture timer1 control register: $13 (under the pulse width measurement mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $13 t1go dec - tm1s0 r/w bit0: timer1 mode select x 0 - 1 r/w bit2: one edge capture x 1 - 1 r/w bit2: double edge capture
SH69P48A 23 8. interrupt four interrupt sources are available on SH69P48A: - adc interrupt - timer0 interrupt - timer1 interrupt - portb/d interrupts (falling edge) interrupt control bits and interrupt service the interrupt control flags are mapped on $00 and $01 of the system register. they can be accessed or tested by the program. those flags are clear to ?0? at initialization by the chip reset. system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $00 iead iet0 iet1 iep r/w interrupt enable flags $01 irqad irqt0 irqt1 irqp r/w interrupt request flags when iex is set to ?1? and the interrupt request is generated (irqx is 1), the interrupt will be activated and vector address will be generated from the priority pla corresponding to the interrupt sources. when an interrupt occurs, the pc and cy flag will be saved into stack memory and jump to interrupt service vector address. after the interrupt occurs, all interrupt enable flags (iex) are clear to ?0? automatically, so when irqx is 1 and iex is set to ?1? again, the interrupt will be activated and vector address will be generated from the priority pla corresponding to the interrupt sources. instruction execution n instruction execution i1 instruction execution i2 interrupt generated interrupt accepted vector generated stacking fetch vector address reset ie.x start at vector address inst.cycle 12345 interrupt servicing sequence diagram interrupt nesting: during the cpu interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. the servicing sequence diagram shows the next interrupt and the ne xt nesting interrupt occurrences. if the interrupt request is ready and the instruction of execution n is ie enabled, then the interrupt will start immediately after the next two instructio n executions. however, if instruction i1 or instruction i2 disables the interrupt request or enable flag, then the interrupt serv ice will be terminated. adc interrupt bit3 (iead) of system register $00 is the adc interrupt enable flag. when the adc conversion is complete, it will generate an interrupt request (irqad = 1), if the adc interrupt is enabl ed (iead = 1), an adc interrupt service routine will start. the adc interrupt can be used to wake the cpu from halt mode. timer (timer0, timer1) interrupt the input clock of timer0 and timer1 are based on system clock or external clock/event t0 input as timer0 source. the timer overflow from $ff to $00 will generate an internal interru pt request (irqt0 or irqt1 = 1), if the interrupt enable flag i s enabled (iet0 or iet1 = 1), a timer interrupt service routine will start. timer interrupt can also be used to wake the cpu from halt mode.
SH69P48A 24 port falling edge interrupt only the digital input port can generate a port interrupt. the analog input cannot generate any interrupt request. port interrupt can be used to wake the cpu from the halt or stop mode. port interrupts by bit only the digital input port can generate a port interrupt. the analog input cannot generate any interrupt request. system register $384, $386: port interrupt enable flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $384 pdien.3 pdien.2 pdien.1 pdien.0 r/w portd interrupt enable flags $386 pbien.3 pbien.2 pbien.1 pbien.0 r/w portb interrupt enable flags system register $385, $387: port interrupt request flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $385 pdif.3 pdif.2 pdif.1 pdif.0 r/w portd interrupt request flags $387 pbif.3 pbif.2 pbif.1 pbif.0 r/w portb interrupt request flags
SH69P48A 25 9. analog/digital converter (adc) the 10 channels and the 10-bit resolution adc converter are implemented in this micro-controller. the adc converter control registers can be used to define the adc channel number, select analog channel, reference voltage and conversion clock, start adc conversion, and set th e end of adc conversion flags. the adc conversion result register byte is read-only. the approach for adc conversion: - set analog channel and select reference voltage. (when using the external reference voltage, keep in mind that any analog input voltage must not exceed v ref ) - operating adc converter module and select the converted analog channels. - set adc conversion clock source. - go/ done = 1, start adc conversion. systems register $14 address bit 3 bit 2 bit 1 bit 0 r/w remarks $14 vrefs - - adcon r/w bit0: set adc module operate bit3: select internal/external reference voltage x - - 0 r/w adc converter module not operating x - - 1 r/w adc converter module operating 0 - - x r/w internal reference voltage (v ref = v dd ) 1 - - x r/w external reference voltage systems register $16 address bit 3 bit 2 bit 1 bit 0 r/w remarks $16 acr3 acr2 acr1 acr0 r/w bit3-0: adc port configuration control 0 0 0 0 r/w see the following table
SH69P48A 26 set analog channels acr3 acr2 acr1 acr0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 pd.1 pd.0 pb3 pb.2 pb.1 pb.0 pa.3 pa.2 pa.1 pa.0 0 0 0 1 pd.1 pd.0 pb.3 pb.2 pb.1 pb.0 pa.3 pa.2 pa.1 an0 0 0 1 0 pd.1 pd.0 pb.3 pb.2 pb.1 pb.0 pa.3 pa.2 an1 an0 0 0 1 1 pd.1 pd.0 pb.3 pb.2 pb.1 pb.0 pa.3 an2 an1 an0 0 1 0 0 pd.1 pd.0 pb.3 pb.2 pb.1 pb.0 an3 an2 an1 an0 0 1 0 1 pd.1 pd.0 pb.3 pb.2 pb.1 an4 an3 an2 an1 an0 0 1 1 0 pd.1 pd.0 pb.3 pb.2 an5 an4 an3 an2 an1 an0 0 1 1 1 pd.1 pd.0 pb.3 an6 an5 an4 an3 an2 an1 an0 1 x 0 0 pd.1 pd.0 an7 an6 an5 an4 an3 an2 an1 an0 1 x 0 1 pd.1 an8 an7 an6 an5 an4 an3 an2 an1 an0 1 x 1 x an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 system register $17 for adc channel selection address bit 3 bit 2 bit 1 bit 0 r/w remarks $17 ch3 ch2 ch1 ch0 r/w bit3-0: select adc channel 0 0 0 0 r/w adc channel an0 0 0 0 1 r/w adc channel an1 0 0 1 0 r/w adc channel an2 0 0 1 1 r/w adc channel an3 0 1 0 0 r/w adc channel an4 0 1 0 1 r/w adc channel an5 0 1 1 0 r/w adc channel an6 0 1 1 1 r/w adc channel an7 1 x x 0 r/w adc channel an8 1 x x 1 r/w adc channel an9 system register $2d - $2f for adc data address bit 3 bit 2 bit 1 bit 0 r/w remarks $2d x x a1 a0 r adc data low nibble (read only) $2e a5 a4 a3 a2 r adc data medium nibble (read only) $2f a9 a8 a7 a6 r adc data high nibble (read only)
SH69P48A 27 systems register $15 address bit 3 bit 2 bit 1 bit 0 r/w remarks $15 go/ done tadc1 tadc0 adcs r/w bit0: set adc conversion time bit2-1: select adc clock period bit3: adc status flag x x x 0 r/w adc conversion time = 204 t ad x x x 1 r/w adc conversion time = 780 t ad x 0 0 x r/w adc clock period t ad = t osc x 0 1 x r/w adc clock period t ad = 4t osc x 1 0 x r/w adc clock period t ad = 8t osc x 1 1 x r/w adc clock period t ad = 16t osc when oscillator type is not selected as 32.768khz crystal oscillator in code option selection. x any value r/w adc conversion time = 12 t ad, adc clock period t ad = t osc when oscillator type is selected as 32.768khz crystal oscillator in code option selection. 0 x x x r/w adc conversion not in progress 1 x x x r/w adc conversion in progress, when adcon = 1 mux 11 10 01 00 mux mux mux tadc1 tadc0 16 t osc 8 t osc 4 t osc t osc t osc en32k en32k 0 1 0 0 1 1 t ad 12 t ad 204 t ad 780 t ad adcs t ad_conversion adc conversion time diagram in the above diagram, en32k equals to 1 wh en the 32.768khz crystal oscillator is se lected as oscillator type in code option; en32k equals to 0 when the 32.768khz crystal oscillator is not selected as oscilla tor type in code option.
SH69P48A 28 a/d coverter v dd portc.1 /v ref select v ref input voltage v ref porta.0/an0 porta.1/an1 porta.2/an2 porta.3/an3 0000 0001 ch3:ch0 portb.0/an4 portb.1/an5 portb.2/an6 portb.3/an7 0110 0111 portd.0/an8 portd.1/an9 1xx0 1xx1 0010 0011 0100 0101 adc converter block diagram notes: - select adc clock period t ad , make sure that 1 s t ad 33.4 s. - when the adc conversion is complete, an adc converter in terrupt occurs (if the adc converter interrupt is enabled). - the analog input channels must have their corresponding pxcr (x = a, b, d) bits selected as inputs. - if an i/o port is selected as analog input, the i/o functions and pull-high resistor will be disabled. - bit go/ done is automatically cleared by hardware when the adc conversion is complete. - clearing the go/ done bit during a conversion will abort the current conversion. - the adc result register will not be updated with the partially completed adc conversion sample. - 4t osc wait is required before the next acquisition is started. - adc converter can keep on working in the halt mode, and would stop automatic while enabling a ?stop? instruction. - adc converter can wake-up the device from the halt mode (if the adc converter interrupt is enabled).
SH69P48A 29 10. pulse width mo dulation (pwm) the SH69P48A consists of two 8+2 pwm modules. the pwm module can provide the pulse width modulation waveform with the period and the duty being controlled, individually. the pwmc is used to control the pwm module operation with proper clocks. the pwmp is us ed to control the period cycle of the pwm module output. and th e pwmd is used to control the duty in the waveform of the pwm module output. system register $20, $21: pwm control register (pwmc) address bit 3 bit 2 bit 1 bit 0 r/w remarks $20, $21 pwmns tnck1 tnck0 pwmn_en r/w bit0: pwmn output enable bit2, bit1: select pwmn clock bit3: set pwmn output mode of duty cycle x x x 0 r/w shared with i/o port (default) x x x 1 r/w shared with pwmn, n = 0 or 1 x 0 0 x r/w pwmn clock = t osc (default) x 0 1 x r/w pwmn clock = 2t osc x 1 0 x r/w pwmn clock = 4t osc x 1 1 x r/w pwmn clock = 8t osc 0 x x x r/w pwmn output normal mode of duty cycle (high active) (default) 1 x x x r/w pwmn output negative mode of duty cycle (low active) n = 0 or 1 the pwm0 output pin is shared with portc.2. the pwm1 output pin is shared with portd.3. system register $22 - $23, $27 - $28: pwm period control register (pwmp) address bit 3 bit 2 bit 1 bit 0 r/w remarks $22, $27 ppn.3 ppn.2 ppn.1 ppn.0 r/w pwmn period low nibble $23, $28 ppn.7 ppn.6 ppn.5 ppn.4 r/w pwmn period high nibble n = 0 or 1 pwm output period cycle = [ ppn.7, ppn.0] x pwmn clock. when [ppn.7, ppn.0] = 00h, pwmn will output gnd if the pwmns bit is set to ?0?. when [ppn.7, ppn.0] = 00h, pwmn will output high level if the pwmns bit is set to ?1?. system register $24 - $26, $29 - $2b: pwm duty control register (pwmd) address bit 3 bit 2 bit 1 bit 0 r/w remarks $24 - - pdf0.1 pdf0.0 r/w pwm0 duty fine tune nibble $25 pd0.3 pd0.2 pd0.1 pd0.0 r/w pwm0 duty low nibble $26 pd0.7 pd0.6 pd0.5 pd0.4 r/w pwm0 duty high nibble $29 - - pdf1.1 pdf1.0 r/w pwm1 duty fine tune nibble $2a pd1.3 pd1.2 pd1.1 pd1.0 r/w pwm1 duty low nibble $2b pd1.7 pd1.6 pd1.5 pd1.4 r/w pwm1 duty high nibble n = 0 or 1 average pwmn output duty cycle = ([pdn.7, pdn.0] + [pdfn.1, pdfn.0]/4) x pwmn clock. if [ppn.7, ppn.0] [pdn.7, pdn.0], pwmn outputs high when the pwmns bit is set to ?0?. if [ppn.7, ppn.0] [pdn.7, pdn.0], pwmn outputs gnd level when the pwmns bit is set to ?1?.
SH69P48A 30 note: - if the i/o port is selected as the pwm output, the i/o functions and pull-high resistor will be disabled. - the writing flow of the pwmn duty control register is described as follows. first set the fine tune nibble, and then the low nibble, and set the high nibble at last. - the writing flow of the pwmn period control register is described as follows. first set the low nibble, and then set the high nibble. - after the high nibble of the pwmn period or duty control register is written, the data are loaded into the re-load counter an d start counting in the next period. - the reading flow of the pwmn period or duty control register is at the reverse direction with that described above. first read the high nibble, and then read the low nibble. - pwm can keep on working in the halt mode, and will stop automatic when the "stop" instruction is enabled. pwmn clock t pwm 01 02 03 04 7d 7e 7f 05 80 ef f0 01 02 03 04 pwmn output (pwmns = 0) pwm output duty cycle = 7fh x t pwm pwmn output (pwmns = 1) pwm output period cycle = f0h x t pwm [ppn.7, ppn.0] = f0h [pdn.7, pdn.0] = 7fh [pdfn.1, pdfn.0] =00h (n = 0 or 1) pwm output example pwmn clock t pwm 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 01 02 03 04 05 06 07 08 write [ppn.7, ppn.0] = 0dh write [pdn.7, pdn.0] = 07h pwmn output (pwmns = 0) period cycle = 0fh x t pwm duty cycle = 06h x t pwm period cycle = 0dh x t pwm duty cycle = 06h x t pwm duty cycle = 07h x t pwm n = 0 or 1 pwm output period or duty cycle changing example
SH69P48A 31 4/10 4/10 4/10 4/10 4/10 5/10 4/10 4/10 4/10 5/10 5/10 5/10 4/10 4/10 5/10 5/10 5/10 5/10 4/10 5/10 pwm modulation period:10 t pwm t pwm modulation cycle 0 [pdfn.1, pdfn.0] = 0 pwm pwm pwm pwm modulation cycle 1 modulation cycle 2 modulation cycle 3 modulation cycle 0 [pdn.7, pdn.0] = 4; [ppn.7, ppn.0] = 10 [pdfn.1, pdfn.0] = 1 [pdfn.1, pdfn.0] = 2 [pdfn.1, pdfn.0] = 3 pwm cycle: 40 t pwm (8+2) bits pwm waveform in the (8+2) bits pwm waveform, a pwm cycle is divided into 4 modulation cycles (cycle 0 - cycle 3), each modulation cycle has certain period decided by period cycle registers (pwmp). the contents of duty cycle register (pwmd) are divided into two parts. the basic part of pwmd is pdn.7 - pdn.0. the extended part is pdfn.1 - pdfn.0. in a pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter [pdfn.1, pdfn .0] (0-3) duty cycle i < [pdfn.1, pdfn.0] ([pdn.7, pdn.0] + 1)/[ppn.7, ppn.0] modulation cycle i (i = 0 - 3) i [pdfn.1, pdfn.0] [pdn.7, pdn.0]/[ppn.7, ppn.0] the modulation period, cycle period and cycle duty of the pwm output signal are summarized in the following table. pwm modulation period pwm cycle period pwm cycle duty [ppn.7, ppn.0] x t pwm 4*[ppn.7, ppn.0] x t pwm (4 x [pdn.7, pdn.0] + [pdfn.1, pdfn.0])/(4 x [ppn.7, ppn.0]) 11. low voltage reset (lvr) the lvr function is to monitor the supply voltage and generate an internal reset in the device. it is typically used in ac line applications or large battery where heavy loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum. the lvr function is selected by the code option. the lvr circuit will feature the following functions when the lvr function is enabled: - generates a system reset when v dd v lvr . - cancels the system reset when v dd > v lvr .
SH69P48A 32 12. watchdog timer (wdt) the watchdog timer is a count-down counter, and its clock source is an independent built-in rc oscillator, so that it will always run even in the stop mode . the watchdog timer will automatically generate a device reset when it overflows. it can be enabled or disabled permanently by using the code option. the watchdog timer control bits ($1e bit2 - bit0) are used to select different overflow frequencies. the watchdog timer overflow flag ($1e bit3) will be automatically set to ?1? by hardware when the watchdog timer overflows. by reading or writing the system register $1e, the watchdog timer should re-count before the overflow happens. system register $1e: watchdog timer (wdt) address bit 3 bit 2 bit 1 bit 0 r/w remarks $1e - wdt wdt.2 - wdt.1 - wdt.0 - r/w r bit2-0: watchdog timer control bit3: watchdog timer overflow flag (read only) x 0 0 0 r/w watchdog timer-out period = 4096ms x 0 0 1 r/w watchdog timer-out period = 1024ms x 0 1 0 r/w watchdog timer-out period = 256ms x 0 1 1 r/w watchdog timer-out period = 128ms x 1 0 0 r/w watchdog timer-out period = 64ms x 1 0 1 r/w watchdog timer-out period = 16ms x 1 1 0 r/w watchdog timer-out period = 4ms x 1 1 1 r/w watchdog timer-out period = 1ms 0 x x x r no watchdog timer overflow reset 1 x x x r watchdog timer overflow, wdt reset happens note: watchdog timer-out period valid for v dd = 5v. 13. halt and stop mode after the execution of halt instruction, SH69P48A will enter the halt mode. in the halt mode, cpu will stop operating. but peripheral circuit (timer0, timer1, adc and watchdog timer) will keep status. after the execution of stop instruction, SH69P48A will enter the stop mode. t he whole chip (including oscillator) will stop operating. but watchdog is still enabled. in the halt mode, SH69P48A can be waked up if any interrupt occurs. in the stop mode, SH69P48A can be waked up if port interrupt occurs or watchdog timer overflow (wdt is enabled). when cpu is awaked from the halt/stop by any interrupt source , it will execute the relevant interrupt serve subroutine at first. then the instruction next to halt/stop is executed. 14. warm-up timer the device has a built-in warm-up timer to eliminate unstable st ate of initial oscillation when o scillator starts oscillating i n the following conditions: power-on reset warm-up time interval: (1) when oscillator range is 30khz - 2mhz, the warm-up counter prescaler divide ratio is 2 12 (4096) (2) when oscillator range is 2mhz -10mhz, the warm-up counter prescaler divide ratio is 2 14 (16384). wake up from stop mode warm-up time interval: (1) in rc oscillator or external clock mode, th e warm-up counter prescaler divide ratio is 2 7 (128). (2) in crystal oscillator or ceramic resonator mode, the warm-up counter prescaler divide ratio is 2 12 (4096).
SH69P48A 33 15. code option oscillator type: op_osc [2:0]: 000 = external clock (select osco pin as portc.0 for a normal i/o port) (default) 001 = internal r osc rc oscillator (4mhz) (select osco pin as port c.0 and osci pin as porte.0 for normal i/o ports) 010 = internal r osc rc oscillator (4mhz) (select osco pin as port c.0 and osci pin as porte.0 for normal i/o ports) 011 = internal r osc rc oscillator (4mhz) (select osco pin as port c.0 and osci pin as porte.0 for normal i/o ports) 100 = external r osc rc oscillator (400khz - 10mhz) (select osco pin as portc.0 for a normal i/o port) 101 = ceramic resonator (400khz - 10mhz) 110= crystal oscillator (400khz - 10mhz) 111 = 32.768khz crystal oscillator oscillator range: op_osc 3: 0 = 2mhz - 10mhz (default) 1 = 30khz - 2mhz watchdog timer: op_wdt: 0 = enable (default) 1 = disable low voltage reset: op_lvr: 0 = disable (default) 1 = enable lvr voltage range: op_lvr0: 0 = high lvr voltage (default) 1 = low lvr voltage chip pin reset: op_rst: 0 = enable chip pin reset (default) 1 = disable chip pin reset (select reset pi n as porte.1 for an open drain output)
SH69P48A 34 in system programming notice for otp the in system programming technology is valid for otp chip. the programming interface of the otp chip must be set on user?s application pcb, and users can assemble all components including the otp chip in the application pcb before programming the otp chip. of course, it?s accessible bonding otp chip only first, and then programming code and finally assembling other components. since the programming timing of programming interface is very sensitive, therefore four jumpers are needed (v dd , v pp , sda, sck) to separate the programming pins from the application circuit as shown in the following diagram. otp chip v pp v dd sck sda gnd to application circuit jumper application pcb otp writer the recommended steps are the followings: (1) the jumpers are open to separate the programming pins from the application circuit before programming the chip. (2) connect the programming interface with otp writer and begin programming. (3) disconnect otp writer and shorten these jumpers when programming is completed. for more detail information, please refer to the otp writer user manual.
SH69P48A 35 instruction set all instructions are one cycle and one-word instructions. the characteristic is memory-oriented operation. 1. arithmetic and logical instruction 1.1. accumulator type mnemonic instruction code function flag change adc x (, b) 00000 0bbb xxx xxxx ac <- mx + ac + cy cy adcm x (, b) 00000 1bbb xxx xxxx ac, mx <- mx + ac + cy cy add x (, b) 00001 0bbb xxx xxxx ac <- mx + ac cy addm x (, b) 00001 1bbb xxx xxxx ac, mx <- mx + ac cy sbc x (, b) 00010 0bbb xxx xxxx ac <- mx + -ac + cy cy sbcm x (, b) 00010 1bbb xxx xxxx ac, mx <- mx + -ac + cy cy sub x (, b) 00011 0bbb xxx xxxx ac <- mx + -ac +1 cy subm x (, b) 00011 1bbb xxx xxxx ac, mx <- mx + -ac +1 cy eor x (, b) 00100 0bbb xxx xxxx ac <- mx ac eorm x (, b) 00100 1bbb xxx xxxx ac, mx <- mx ac or x (, b) 00101 0bbb xxx xxxx ac <- mx | ac orm x (, b) 00101 1bbb xxx xxxx ac, mx <- mx | ac and x (, b) 00110 0bbb xxx xxxx ac <- mx & ac andm x (, b) 00110 1bbb xxx xxxx ac, mx <- mx & ac shr 11110 0000 000 0000 0 -> ac [3], ac[0] -> cy; ac shift right one bit cy 1.2. immediate type mnemonic instruction code function flag change adi x, i 01000 iiii xxx xxxx ac <- mx + i cy adim x, i 01001 iiii xxx xxxx ac, mx <- mx + i cy sbi x, i 01010 iiii xxx xxxx ac <- mx + -i +1 cy sbim x, i 01011 iiii xxx xxxx ac, mx <- mx + -i +1 cy eorim x, i 01100 iiii xxx xxxx ac, mx <- mx i orim x, i 01101 iiii xxx xxxx ac, mx <- mx | i andim x, i 01110 iiii xxx xxxx ac, mx <- mx & i 1.3. decimal adjustment mnemonic instruction code function flag change daa x 11001 0110 xxx xxxx ac, mx <- decimal adjust for add. cy das x 11001 1010 xxx xxxx ac, mx <- decimal adjust for sub. cy
SH69P48A 36 2. transfer instruction mnemonic instruction code function flag change lda x (, b) 00111 0bbb xxx xxxx ac <- mx sta x (, b) 00111 1bbb xxx xxxx mx <- ac ldi x, i 01111 iiii xxx xxxx ac, mx <- i 3. control instruction mnemonic instruction code function flag change baz x 10010 xxxx xxx xxxx pc <- x, if ac = 0 bnz x 10000 xxxx xxx xxxx pc <- x, if ac 0 bc x 10011 xxxx xxx xxxx pc <- x, if cy = 1 bnc x 10001 xxxx xxx xxxx pc <- x, if cy 1 ba0 x 10100 xxxx xxx xxxx pc <- x, if ac (0) = 1 ba1 x 10101 xxxx xxx xxxx pc <- x, if ac (1) = 1 ba2 x 10110 xxxx xxx xxxx pc <- x, if ac (2) = 1 ba3 x 10111 xxxx xxx xxxx pc <- x, if ac (3) = 1 call x 11000 xxxx xxx xxxx st <- cy, pc +1 pc <- x (not include p) rtnw h, l 11010 000h hhh llll pc <- st; tbr <- hhhh, ac <- llli rtni 11010 1000 000 0000 cy, pc <- st cy halt 11011 0000 000 0000 stop 11011 1000 000 0000 jmp x 1110p xxxx xxx xxxx pc <- x (include p) tjmp 11110 1111 111 1111 pc <- (pc11-pc8) (tbr) (ac) nop 11111 1111 111 1111 no operation where, pc program counter i immediate data ac accumulator logical exclusive or -ac complement of accumulator | logical or cy carry flag & logical and mx data memory bbb ram bank p rom page st stack tbr table branch register
SH69P48A 37 electrical characteristics absolute maximum ratings* dc supply voltage . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v input/output voltage . . . . . . . . . . gnd-0.3v to v dd + 0.3v operating ambient temperature . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . -55c to +125c *comments stresses exceed those listed under " absolute maximum ratings " may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v dd = 2.4 - 5.5v, gnd = 0v, t a = 25c, unless otherwise specified) parameter symbol min. typ. ? max. unit condition operating voltage v dd 4.5 5.0 5.5 v 30khz f osc 10mhz operating voltage v dd 2.4 5.0 5.5 v 30khz f osc 4mhz - 3 4.5 ma f osc = 10mhz all output pins unload, execute nop instruction, wdt off, adc disable, lvr off. v dd = 5.0v operating current i op - 2 3 ma f osc = 4mhz all output pins unload, execute nop instruction, wdt off, adc disable, lvr off. v dd = 5.0v - - 1.5 ma f osc = 10mhz all output pins unload (halt mode), wdt off, adc disable, lvr off. v dd = 5.0v stand by current (halt) i sb1 - - 1 ma f osc = 4mhz all output pins unload (halt mode), wdt off, adc disable, lvr off. v dd = 5.0v stand by current (stop) i sb2 - - 1 a all output pins unload (stop mode), wdt off, adc disable, lvr off. v dd = 5.0v wdt current i wdt - - 20 a all output pins unload (stop mode), wdt on, adc disable, lvr off, v dd = 5.0v input low voltage v il1 gnd - 0.3 x v dd v i/o ports input low voltage v il2 gnd - 0.2 x v dd v reset , t0, t1, osci input high voltage v ih1 0.7 x v dd - v dd v i/o ports input high voltage v ih2 0.8 x v dd - v dd v reset , t0, t1, osci input leakage current i il -1 - 1 a input pad, v in = v dd or gnd pull-high resistor r ph 10 30 50 k ? v dd = 5.0v, v in = gnd output leakage current i ol -1 - 1 a open drain output, v dd = 5.0v v out = v dd or gnd output high voltage v oh v dd - 0.7 - - v i/o ports, pwm0 & 1, i oh = -10ma, v dd = 5.0v output low voltage v ol - - gnd + 0.6 v i/o ports, pwm0 & 1, i ol = 20ma, v dd = 5.0v ? : data in ?typ.? column is at 5.0v, 25c, unless otherwise specified. maximum value of the supply current to v dd is 100ma. maximum value of the output current from gnd is 150ma.
SH69P48A 38 ac electrical characteristics (v dd = 2.4v - 5.5v, gnd = 0v, t a = 25c, f osc = 30khz - 10mhz, unless otherwise specified.) parameter symbol min. typ. max. unit condition reset pulse width t reset 10 - - s v dd = 5.0v wdt period t wdt 1 - - ms v dd = 5.0v frequency variation |? f|/f - - 15 % external rc oscillator |f(5.0v) - f(2.4v)|/f(5.0v) internal rc frequency variation f osc 3.80 4.00 4.20 mhz v dd =5v, t a = 5c - 45c instruction cycle time t cy 0.4 - 133.4 s f osc = 30khz - 10mhz t0 input width t iw (t cy + 40)/n - - ns n = prescaler divide ratio input pulse width t ipw t iw /2 - - ns timing waveform (a) system clock timing waveform t1 t2 t3 t4 t5 t6 t7 t8 t1 t2 t3 t4 f osc system clock t cy (b) t0 input waveform t iw t ipw(l) t ipw(h) t0 input signal
SH69P48A 39 adc converter electrical characteristics ( v dd = 2.4v - 5.5v, gnd = 0v, t a = 25c, f osc = 30khz - 10mhz, unless otherwise specified.) parameter symbol min. typ. max. unit condition resolution nr - - 10 bit gnd v ain v ref reference voltage v ref 2.4 - v dd v adc input voltage v ain gnd - v ref v adc input resistor r ain 2000 - - k ? v in = 5.0v adc conversion current i ad - 500 1000 a adc converter module operating, v dd = 5.0v nonlinear error e nl - - 2 lsb v ref = v dd = 5.0v full scale error e f - - 1 lsb v ref = v dd = 5.0v offset error e z - - 1 lsb v ref = v dd = 5.0v total absolute error e ad - 1 2 lsb v ref = v dd = 5.0v adc clock period t ad 1 - 33.4 s f osc = 30khz - 10mhz adc conversion time t cnv1 - 204 - t ad set adcs = 0 adc conversion time t cnv2 - 780 - t ad set adcs = 1 low voltage reset electrical characteristics ( gnd = 0v, t a = 25c, f osc = 32.768khz - 10mhz, unless otherwise specified.) parameter symbol min. typ. max. unit condition lvr voltage (1) v lvr1 3.8 - 4.2 v lvr enable lvr voltage (2) v lvr2 2.3 - 2.7 v lvr enable lvr voltage pulse width t lvr 500 - - sv dd v lvr
SH69P48A 40 rc oscillator charact eristics graphs (fo r reference only) internal rc oscillator charact eristics graphs (operating voltage vs. frequency): operating voltage vs. frequency 3.950 4.000 4.050 4.100 4.150 4.200 2468 operating voltage: v dd (v) frequency: fosc (mhz) external rc oscillator charact eristics graphs (external resistor vs. frequency): rc oscillator resistor vs. frequency 0.1 1 10 0 40 80 120 160 200 240 280 320 360 400 440 480 520 rc oscillator resistor: rosc (k ? ) frequency: fosc (mhz)
SH69P48A 41 application circuits (for reference only): (1) operating voltage: 5.0v (2) oscillator: internal rc 4mhz (3) porta.0 - 1: temperature analog input; porta.2: current analog input; porta.3: battery type analog input; portb.0 - 3: battery voltage analog input; portd.0 - 1, portc.0, porte.0: battery charging on/off output; portc.1: external reference voltage input; portc.2: charging current control output; portc.3, portd.2 - 3: led display output portd.2 portd.3 pwm0 portc.3 reset gnd an.0 an.1 an.2 an.3 SH69P48A portd.1 portd.0 v ref portc.0 porte.0 v dd an.7 an.6 an.5 an.4 8.2k +5v +5v +12v +12v +5v +12v +12v +5v bat3v r1 r2 r3 d1 47k 0.1u 1 3 2 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 sw1 r21 r22 r6 r5 d2 q1 l1 r7 104 100uf r9 r10 r11 r12 q5 q6 q7 q8 q2 q3 q4 d3 d4 d5 d6 d7 d8 d9 d10 bat4 bat3 bat1 bat2 r13 r14 r15 r16 r17 r18 r4 r8 r20 rt2 bat4v bat2v bat1v bat2v 12 r23 11 r24 bat1v bat3v bat4v rt1 r19 +5v
SH69P48A 42 bonding diagram SH69P48A 2 11 4 1 13 14 15 16 12 3 24 23 reset gnd portc0 porte.0 v dd v dd 2588um 2040um gnd (0,0) y x 22 21 20 19 18 17 5 6 7 8 9 10 portc.3 portc.2 portd.3 portd.2 portd.1 portd.0 portc.1 gnd porta.0 porta.1 porta.2 porta.3 portb.0 portb.1 portb.2 portb.3 gnd substratum connects to ground. pad location unit: m pad no. designation x y pad no. designation x y 1 reset -880.55 992.6 13 v dd 763.4 -919.7 2 gnd -868.3 -1004.35 14 v dd 830.8 -790.85 3 gnd -886 -1126.1 15 porte.0 882.4 -596.8 4 porta.0 -714.45 -1158 16 portc.0 882.4 396.35 5 porta.1 -484.65 -1158 17 gnd 683.8 1158 6 porta.2 -350.65 -1158 18 portc.1 538.35 1158 7 porta.3 -120.85 -1158 19 portd.0 307.45 1158 8 portb.0 13.15 -1158 20 portd.1 173.45 1158 9 portb.1 242.95 -1158 21 portd.2 -57.45 1158 10 portb.2 376.95 -1158 22 portd.3 -191.45 1158 11 portb.3 606.75 -1158 23 portc.2 -422.35 1158 12 gnd 771.3 -1126.6 24 portc.3 -556.35 1158 note: the all gnd pins must be connected together outside the chip.
SH69P48A 43 ordering information part no. package SH69P48Ah chip form SH69P48A/020du 20l dip SH69P48Am/016mu 16l sop SH69P48Am/020mu 20l sop
SH69P48A 44 package information p-dip 20l outline dimensions unit: inches/mm 110 11 20 d e 1 s a 2 a l c e e a b 1 b e 1 base plane a 1 seating plane symbol dimensions in inches dimensions in mm a 0.175 max. 4.45 max. a 1 0.010 min. 0.25 min. a 2 0.138 0.008 3.50 0.20 0.018+0.004 0.46+0.10 b -0.002 -0.05 0.060+0.004 1.52+0.10 b 1 -0.002 -0.05 0.010+0.004 0.25+0.10 c -0.002 -0.05 d 1.026 typ. (1.046 max.) 26.06 typ. (26.57 max.) e 0.300 0.010 7.62 0.25 e 1 0.250 typ. (0.262 max.) 6.35 typ. (6.65 max.) e 1 0.100 typ. 2.54 typ. l 0.130 0.010 3.30 0.25 0 - 15 0 - 15 e a 0.345 0.035 8.76 0.89 s 0.078 max. 1.98 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash.
SH69P48A 45 sop 20l (w.b.) outline dimensions unit: inches/mm 1 l l e c 10 see detail f detail f 11 20 e 1 e 1 s seating plane ~ ~ ~ b e h e d a 1 a 2 a d y e symbol dimensions in inches dimensions in mm a 0.106 max. 2.69 max. a 1 0.004 min. 0.10 min. a 2 0.092 0.005 2.33 0.13 0.016+0.004 0.41+0.10 b -0.002 -0.05 0.010+0.004 0.25+0.10 c -0.002 -0.05 d 0.500 0.02 12.80 0.51 e 0.295 0.010 7.49 0.25 e 0.050 0.006 1.27 0.15 e 1 0.376 nom. 9.50 nom. h e 0.406 0.012 10.31 0.31 l 0.032 0.008 0.81 0.20 l e 0.055 0.008 1.40 0.20 s 0.042 max. 1.07 max. y 0.004 max. 0.10 max. 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
SH69P48A 46 sop 16l (w.b.) outline dimensions unit: inches/mm 1 l l e c 8 see detail f 9 16 e 1 e 1 s seating plane ~ ~ ~ b e h e d a 1 a 2 a d y e detail f symbol dimensions in inches dimensions in mm a 0.175 max. 2.79 max. a 1 0.004 min. 0.10 min. a 2 0.092 0.005 2.33 0.13 0.016+0.004 0.41+0.10 b -0.002 -0.05 0.010+0.004 0.25+0.10 c -0.002 -0.05 d 0.400 0.014 10.16 0.36 e 0.295 0.010 7.49 0.25 e 0.050 0.006 1.27 0.15 e 1 0.376 nom. 9.55 nom. h e 0.406 0.012 10.31 0.31 l 0.030 0.008 0.76 0.20 l e 0.055 0.008 1.40 0.20 s 0.033 max. 0.84 max. y 0.004 max. 0.10 max. 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
SH69P48A 47 data sheet revision history version content date 2.1 package information update sep. 2008 2.0 update ordering information mar. 2008 1.0 original dec. 2007

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